Shekhar Pandey
I'm an ML systems engineer at AMD, working on large-scale MoE training, LLM inference, and low-precision GPU kernels. I've delivered MXFP8 training and serving optimizations across AMD CDNA3/CDNA4 systems, scaled DeepSeek-V3 to 1,024 GPUs, and contributed performance improvements to PyTorch, TorchAO, and vLLM.
GitHub · LinkedIn · X · LeetCode · Resume · Email
Ragged MXFP8 Weight Gradients: A FlyDSL Grouped GEMM on MI355X
September 2026The weight gradient is the one MoE grouped GEMM whose ragged dimension sits inside the reduction. How a FlyDSL kernel for it climbed from 161 to 2,174 TFLOP/s at one shape on MI355X (2,522 at the 671B shapes), about 2.1 to 2.5× the BF16 grouped GEMM on pre-quantized operands. The optimizations that worked, the ones that didn't, and the power wall at the top.
Inside the CDNA5 Tensor Data Mover
September 2026CDNA5 adds a small DMA engine that copies tiles of a tensor from global memory straight into LDS, without the shader core computing a single address. What it is, how you drive it, how the descriptor describes a copy, and how the counter lets the copy overlap the math. Checked against an MI450.
Beating torch.relu with FlyDSL: A Hands-On Guide to Bandwidth-Bound Kernels
August 2026Simon Boehm's CUDA matmul post, but in one dimension. Writing the simplest GPU kernel there is in AMD's FlyDSL, then taking it from 2.9 to 7.2 TB/s on an MI350X — 1.04x torch.relu at the tuned shape, 1.28x at its best. Five versions with the code, what each optimization was actually worth, the two that measured negative, and the testing discipline a layout DSL asks for.
MXFP8: Microscale Floating Point 8 — How Block-Level Scaling Makes 8-Bit Training Work
June 2026A from-first-principles look at the MXFP8 datatype: why regular FP8 isn't enough, how a shared power-of-two scale per 32-element block restores FP32-like reach, the hardware plumbing on AMD CDNA4, and why the block size is 32.
Occupancy Math on the AMD MI355X (CDNA4): A From-First-Principles Guide
May 2026A from-first-principles guide to wavefront occupancy on AMD's MI355X (CDNA4): the hardware resource budget, the four limiters that cap it, worked MXFP8 GEMM examples, and why peak throughput often lives at low occupancy.